Andrew R. Pleszkun

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This paper describes and evaluates solutions to the precise interrupt problem in pipelined processors. An interrupt is precise if the saved process state corresponds with a sequential model of program execution where one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an(More)
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and only committed if the original predictions were correct. There are a number of other ways that processor resources could be used, such as threading or eager execution. As the use of(More)
As processor performance continues to improve, more emphasis must be placed on the performance of the memory system. In this paper, a detailed characterization of data cache behavior for individual load instructions is given. We show that by selectively applying cache line allocation according the characteristics of individual load instructions, overall(More)
Fibre channel has long dominated the realm of storage area networks (SAN’s). However, with increased development and refining, iSCSI is fast becoming an equal contender, which is causing many companies to reconsider how future storage networks shall be implemented. In addition to reduced costs and a unified network infrastructure, iSCSI allows for the(More)
Absm~-PIPE (Parallel Instructions and Pipelined Execution) is a research vehicle for stud)~ng high performance VLSI architectures and organizations. Its principal features are: 1) it is pipelined, 2) it makes extensive use of architectural queues, 3) it is capable of a decoupled mode of operation where two processors cooperate in executing the same task and(More)
In this paper a technique for generating consistent, reproducible traces with about an order of magnitude better compression than standard general-purpose compression programs is described. With this approach, the trace is read once, an intermediate form is generated and then read as the input to the second pass over the address stream. No program source(More)
This paper describes a single chip Multiple Instruction Stream Computer (MIX) capable of extracting instruction level p&llelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conff ict-free message passing system(More)