Andrew J. Blanksby

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A 1024-b, rate-1/2, soft decision low-density paritycheck (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding(More)
The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog(More)
A High Data Rate (HDR) system has been proposed for providing downlink wireless packet service by using a channel-aware scheduling algorithm to transmit to users in a time-division multiplexed manner. In this paper, we propose using multiple antennas at the transmitter and/or at the receiver to improve performance of an HDR system. We consider the design(More)
With regard to obstacle avoidance, a paradigm shift from technology centered solutions to technology independent solutions is taking place. This trend also gives rise to a shift from function specific solutions to multifunctional solutions. A number of existing approaches will be reviewed and a case study of a biologically inspired insect vision model will(More)
This paper presents a decision feedback equalizer (DFE) for a high-speed packet modem utilizing the normalized least mean squared (NLMS) tap update algorithm. The equalizer supports up to 43.2 Mbps uncoded data over a wireless channel with a 10% training preamble (48 Mbps with no training). In this work the rapid convergence of the NLMS algorithm is(More)
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