Andrew Ferko

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Delay testing has become increasingly essential as chip geometries shrink [1,2,3]. Low overhead or cost effective delay test methodology is successful when it results in a minimal number of effective tests and eases the demands on an already burdened IC design and test staff. This paper describes one successful method in use by IBM ASICs that resulted in a(More)
We introduce a new concept for a geometrically based feature preserving reconstruction technique of n-dimensional scattered data. Our goal is to generate an n-dimensional triangulation, which preserves the high frequency regions via local topology changes. It is the generalization of a 2D reconstruction approach based on data-dependent triangulation and(More)
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