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LegUp: high-level synthesis for FPGA-based processor/accelerator systems
TLDR
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. Expand
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LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
TLDR
We introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. Expand
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  • PDF
A Survey and Evaluation of FPGA High-Level Synthesis Tools
  • R. Nane, V. Sima, +9 authors K. Bertels
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of…
  • 1 October 2016
TLDR
High-level synthesis (HLS) is increasingly popular for the design of high performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. Expand
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Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
TLDR
We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. Expand
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Modulo SDC scheduling with recurrence minimization in high-level synthesis
TLDR
We propose a novel modulo scheduler based on an SDC formulation that includes a backtracking mechanism to properly handle multiple scheduling constraints and still achieve the minimum possible initiation interval. Expand
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Impact of FPGA architecture on resource sharing in high-level synthesis
TLDR
Resource sharing is a key area-reduction approach in high- level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. Expand
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From software to accelerators with LegUp high-level synthesis
TLDR
This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning. Expand
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Low-cost hardware profiling of run-time and energy in FPGA embedded processors
TLDR
This paper introduces a low-overhead hardware profiling architecture, called LEAP, that attains real-time cycle and energy profiles of an FPGA-based soft processor that is both area- and power-efficient. Expand
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Multi-pumping for resource reduction in FPGA high-level synthesis
TLDR
We propose a new approach to resource sharing using multi-pumping that allows multiple operations to be performed by a single functional unit in one clock cycle. Expand
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The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs
TLDR
We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated FPGA hardware. Expand
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