Andrew Bardsley

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SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective , albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed(More)
This paper introduces several new component clustering techniquesfor the optimization of asynchronous systems. In particular, novel"Burst-Mode aware" restrictions are imposed to limit the cluster sizesand to ensure synthesizability. A new control specification language,CH, is also introduced which facilitates the manipulation and optimizationof handshake(More)
—This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise handshake interleaving and enclosure by separating out control 'go' and 'done' signalling into separate channels rather than using different phases of the asynchronous handshake. This(More)
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthesis paradigm that compiles transparently a system specification written in a high-level language into a network of pre-designed handshaking modules. The transparency is provided by(More)
Several approaches have been proposed for the syntax-directed compilation of asynchronous circuits from high-level specification languages, such as Balsa [1] and Tan-gram [13, 10]. Both compilers have been successfully used in large real-world applications; however, in practice , these methods suffer from significant performance overheads due to their(More)