Andres Viveros-Wacher

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The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a(More)
Higher data rates in high speed input/output (HSIO) links demand more equalization (EQ) complexity, leading to an ever larger number of possible combinations of EQ settings. Finding the optimal set of EQ parameters through exhaustive methods is prohibitive given the time-to-market requirements. This paper presents a methodology to design a statistically(More)
There is an increasingly higher number of mixed-signal circuits within microprocessors. A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links is critical to provide a release qualification decision. One of the major challenges in HSIO electrical validation is the physical layer (PHY) tuning(More)
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