Andrei Vladimirescu

Learn More
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V DD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as(More)
Between July and October 1996, a West Nile (WN) fever epidemic occurred in the southern plain and Danube Valley of Romania and in the capital city of Bucharest, resulting in hundreds of neurologic cases and 17 fatalities. In early October 1996, entomologic and avian investigations of the epidemic were conducted in the city of Bucharest and nearby rural(More)
– As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including(More)
Planar fully-depleted SOI technology with ultra-thin body and buried oxide presents a platform for an energy-efficient design in deeply scaled technologies without major changes in the bulk-CMOS design infrastructure. Good control of short-channel effects with thin transistor body offers a possibility to reduce the supply voltage. Thin buried oxide provides(More)
—Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a(More)
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V DD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM(More)
Contribution à l'élaboration de méthodologies et d'outils d'aide à la conception de systèmes multi-technologiques Soutenance le 27 novembre 2003 devant le jury composé de A mes parents, à mes soeurs, à mon frère, et à mon épouse Houda 3 Ecole Nationale Supérieure des Télécommunications REMERCIEMENTS Le travail présenté dans cette thèse a été effectué au(More)