Andreas Wassatsch

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In this paper, we propose a 12.8Gbit/s Triple DES processor using 0.6um/5V AMS. A conventional static CMOS implementation cannot fulfill the requirements of high throughput digital designs. In contrast, dynamic logic has the principle advantage of speeding-up logic designs. In particular True Single Phase Clock (TSPC) Logic shows a robust cell(More)
The CORDIC algorithm is used in many fields of signal processing for computation of elementary functions. Its main advantages are versatility and simplicity. When implemented in a word parallel pipeline it yields the highest possible throughput. However, this solution is accompanied with increased hardware complexity and chip area requirements. The goal of(More)
Dynamic circuit implementation style is a common technique for high performance applications like microprocessor or DSP design. Due to the different characteristics of the dynamic cells compared with static CMOS circuits we need adapted synthesis methods. Unfortunately, there is no standard CAD support for dynamic CMOS logic until now so the design of these(More)
High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA(More)
For high performance designs, dynamic logic styles are in the focus due to the promising high reachable frequencies. True Single Phase Clock (TSPC) logic yields easy to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. Asynchronous logic has the potential to solve(More)
In this application report we describe the development process of a new concept for implementing artificial neural networks. Based on the idea to utilize a previously developed concept of digit online calculation of arithmetic functions we start the development with high level simulations of Matlab network models. We also use these simulation models to(More)
In this paper we describe an approach for using the true single phase clock (TSPC) circuit style for the implementation of a scalable, pre-loadable pre-scaler. By utilization of a signed digit (SD) based redundant adder cell the execution of the necessary addition operation can be performed in only one clock cycle, independent from the length of the applied(More)