Andreas Schallenberg

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Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for(More)
High level description languages and tools lack appropriate support to specify reconfigurable systems. We propose a methodology for partially self-reconfigurable systems, which consists of a SystemC based language, simulation abilities and the perspective of automated synthesis. We introduce a configuration management infrastructure, which frees designers(More)
This paper presents a new approach to design embedded systems based on dynamic partial reconfigurable FPGAs. The approach is intended to allow designing of systems with runtime reconfiguration without explicit specification by the designer. The design entry point is the HDL OSSS, a SystemC extension allowing for synthesizable object orientation and(More)
In this paper we will present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems based on the modelling language SystemC. The methodology and tools will enable early integration and exploration of system specifications using different Models of Computation as well as(More)
Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task clue to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making(More)
Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access(More)