- Full text PDF available (1)
In this paper, we demonstrate a fully differential transimpedance amplifier (TIA) with 49 dB-ohm transimpedance, greater than 50 GHz bandwidth, and input-referred current noise less than 30pA//spl radic/(Hz).
The combination of device speed (f/sub T/, f/sub max/>150 GHz) and breakdown voltage (V/sup bcco/ of about 10 V), makes the double heterojunction InP-based HBT (D-HBT), a very attractive technology to implement the most demanding analog functions of 40 Gb/s transceivers. This is illustrated by the performance of a number of InP D-HBT circuits including… (More)
In this paper, we describe an InGaAs/InP heterostructure bipolar transistor differential transimpedance amplifier with high bandwidth of 47 GHz and high gain of 56 dB-ohms.
Low-density parity-check (LDPC) codes based on structured parity check matrices are widely used due to their favorable implementation properties. Often, however, the convergence threshold is optimized based on the general LDPC code ensemble (i.e., the degree profile only) without taking into account the imposed structure, leading to a mismatch of… (More)
1.3 - 1.55μm wavelength 20 Gbit/s MSM-HEMT and 10 Gbit/s PIN-HEMT photoreceivers have been monolithically integrated on GaAs substrates using a 0.3 μm gate length AlGaAs/GaAs HEMT process. The In/sub 0.53/Ga/sub 0.47/As MSM and PIN photodiodes grown on GaAs have nearly identical characteristics to photodiodes grown on InP.
A 12 GS/s track-and-hold amplifier (THA) for a DSP-based electrical polarization-mode dispersion compensator (e-PMDC) in a 10 GHz optical receiver, featuring a total harmonic distortion (THD) compatible with 6 bit operation on 1 V/sub p-p/ differential input range at -5.2 V supply, has been designed and fabricated in InP/InGaAs/InP double-heterojunction… (More)
A 5-b flash ADC with a closed-loop THA is implemented in 0.18-mum SiGe BiCMOS. A global shunt feedback THA and a current-weighted comparator allow the ADC to achieve wide resolution bandwidth of 6.5 GHz and high sampling rate up to 24 GS/s. The ADC shows an SNDR of 28 dB and an SFDR of 36 dB with a 1 GHz input sampled at 16 GS/s. It consumes 3.3 W from… (More)
In this paper, we consider iterative detection in combination with an outer low-density parity-check (LDPC) code, and present new EXIT curves that help to optimize the decoding schedule among these blocks. For this, we compute a set of (inner) detector and variable node decoder curves depending on whether or not the detector update is included into the… (More)