Andreas Iliopoulos

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The sequential execution of processing elements by time-multiplexing FPGA resources using single-island partial reconfiguration allows for resource-efficient designs in comparison to static FPGA implementations. Designing a processing chain for such a system requires the chain to be partitioned into reconfigurable modules, which can be sequentially(More)
Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set(More)
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