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Modeling neural tissue is an important tool to investigate biological neural networks. Until recently, most of this modeling has been done using numerical methods. In the European research project ”FACETS” this computational approach is complemented by different kinds of neuromorphic systems. A special emphasis lies in the usability of these systems for(More)
In this article, we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from(More)
In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart of this system lies a mixed-signal chip, with analog implementations of neurons and synapses and digital transmission of action potentials. Major advantages of this emulation device, which has been(More)
We describe an accelerated hardware neuron being capable of emulating the adap-tive exponential integrate-and-fire neuron model. Firing patterns of the membrane stimulated by a step current are analyzed in transistor level simulations and in silicon on a prototype chip. The neuron is destined to be the hardware neuron of a highly integrated wafer-scale(More)
This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI model of a spiking neural network. The artificial synapses are based on an implementation of spike time dependent plasticity (STDP). In the biological specimen, STDP is a mechanism acting locally in each synapse. The presented(More)
— In this paper, we present a system architecture currently under development that will allow very large (>10 6 neu-rons, >10 9 synapses) reconfigurable networks to be built, in the form of interlinked dies on a single wafer. Reconfigurable routing and complex adaptation/plasticity across several timescales in neurons and synapses allow for the(More)
— This paper presents a platform for the parallel operation of VLSI neural networks allowing to seamlessly map neural network topologies on distributed resources. The scalable approach provides fast isochronous communication channels transporting the neuron signals between single network modules. The network modules are printed circuit boards hosting a(More)
ANCs (two under each housing) DNC (under heat sink) FPGA board with comm. interfaces Power supply for FPGA board Fig. 1. The demonstrator system: eight ANCs, DNC and FPGA board. This demonstration is based on the wafer-scale neuromophic system presented in [1], [2] and [3]. One wafer of this system contains 384 analog network chips (ANC) for a total of 40 M(More)