Andrea Panigada

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Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This(More)
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches [1,2]. It is the first IC implementation of HDC, and the results demonstrate that HDC(More)
A major problem in oversampling digital-to-analog converters and fractional-N frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals passing through nonlinear analog components. This paper presents a(More)
The digitally-enhanced high speed (200 Msps) analog-to-digital converter (ADC) includes dynamically configurable digital signal post-processing options such as a digital down-converter for In-phase and Quadrature signal detection (I/Q demodulation), digital decimation filter for achieving higher signal-to-noise ratio (SNR), and digital beamforming that(More)
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