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—An energy detector designed in a 0.18μm CMOS technology and intended for a non-coherent impulse-radio UWB receiver is presented in this paper. The proposed circuit exploits the quadratic current characteristic of saturated MOS transistors to square input pulses that cover the whole UWB bandwidth. The integral is computed with a Gm-C architecture connected(More)
In this work we present a full analog turbo decoder for hard-disk EPR-IV read channels in CMOS technology. The design is based on a current-mode approach developed by Loeliger et al. [1], for the analog implementation of sum-product algorithms. The circuits main attractions are the coding gain offered by turbo codes over the uncoded EPR-IV channel, and the(More)
— This paper presents an all-analog iterative decoding network for an EPR4 magnetic recording system. A powerful serially concatenated architecture is considered, consisting of a simple outer code, an interleaver with reasonable size and a rate 1 EPR4 channel as inner code. The analog chip design is based on analog 0.18µm CMOS technology. Simulation results(More)
—In this paper, we present an all-analog implementation of the rate-1/3, block length 40, universal mobile telecommunications system (UMTS) turbo decoder. The prototype was designed and fabricated in 0.35 m complementary metal–oxide–semiconductor technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which(More)