Andrea Malignaggi

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This paper presents the extraction techniques of the RF feeding structures for accurate modeling of on-chip passive and active components. The presented techniques have been applied for a group of test structures realized in a 90 nm CMOS process and validated through measurements up to 100 GHz. Feeding structures comprising RF probing pads, pad to the(More)
In this work an on-off shift keying transmitter front-end for 60 GHz wireless communication is presented. To enhance the transmitter performance, a novel modulator topology is implemented. Designed and fabricated in 90 nm CMOS, the transmitter occupies 0.38 mm<sup>2</sup> and provides 8 dBm output power with 36 mW DC power consumption. The transmitter(More)
This work investigates the design of two different coplanar transmission lines and their application at millimeter wave frequencies up to 100 GHz. The coplanar structure has been selected to improve the grounding and also to remove the effect of the fillers on the transmission line. The two transmission lines differ by their bottom metal layer pattern. In(More)
This paper presents a fully integrated 60 GHz two stage power amplifier for wireless applications using common source topology and power combining. The PA is implemented in a 90 nm low power CMOS technology. The output power of the amplifier has been improved with the help of Wilkinson power combining technique. Also the Wilkinson power combiner has been(More)
This paper presents the small signal characterization of nMOS transistors in 90 nm CMOS technology. Two different transistor widths are characterized based on the measurement results up to 110 GHz. The widths of the transistors are optimized for low noise and power amplifier applications at 60 GHz. For the characterization purpose, the on-chip feeding(More)
This paper presents a new technique for transformer based millimeter-wave power amplifier design. For this purpose a new scalable model for on-chip transformers is introduced. The modeling technique is also validated for 90 nm LP CMOS technology by comparing measured and simulated results. Due to high accuracy and scalability of the model, a faster and more(More)
This work presents the design of a Q-band static frequency divider with quadrature signal output suitable for 60 GHz application. The RF performance improvement and power consumption reduction is achieved by using inductive peaking, resistor splitting techniques as well as proper transistor sizing. The static frequency divider is realized in a 90 nm CMOS(More)
This paper presents the design procedure of a fully integrated 60 GHz double balanced Gilbert cell up-conversion mixer, implemented in 90 nm LP CMOS technology. The mixer is designed for wideband performance to cover the four bands of the IEEE802.15.3c standard. The up-converter achieves a flat conversion gain of -2 dB and an output power of -9 dBm at 1 dB(More)
In this work, a Q-band injection-locked frequency divider (ILFD) has been implemented in 90 nm CMOS technology. An ILFD topology of transformer-based dual-path injection was proposed to maximize the power gain of the injection path and improve the locking range of the ILFD. On-wafer measurements showed that with 0 dBm input power, the proposed ILFD achieves(More)
The design of an IQ-Demodulator for the IEEE 802.15.3c standard is presented. The design is targeted for low noise, low power consumption and small chip area. The IQ-Demodulator is fabricated in a 90 nm CMOS technology; it converts down a 2 GHz wide channel at around the IF of 20 GHz to the neighborhood of the zero frequency. New current bleeding network(More)