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— Design strategies for power effective medium/high resolution Successive-Approximation ADC are discussed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need using non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain(More)
This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-lm CMOS technology, achieves a(More)
Cascade scheme of single order incremental modulators that obtain high-order architectures are studied. The use of high-order obtains a high number of bit with a small number of clock periods. Moreover, it is possible to use multi-bit modulators in the last stages of the chain. The requests of low gain error in the first stages of the cascade are satisfied(More)
This paper describes an incremental converter based on a second order RD modulator. The scheme uses a 3-bit DAC with inherent linearity, an optimal reset of integrators, and gives rise to an effective offset cancellation with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 lm CMOS technology, obtains 1.5-lV(More)
— A method for cancelling the replica image limiting the chopper stabilization technique is presented. The modulation of the 1/f noise at the chopping frequency and its multiple are conventionally reduced by a low-pass filter and, possibly by a notch filter. The method presented here combines the second chopper and the notch filter by using a simple SC(More)
This paper presents an incremental converter, based on a second order scheme, able to achieve 19 bit of resolution with 512 clock periods. The design avoids an initial error by an optimal reset of the two integrators, uses a 3-bit quantizer that enhances the resolution, and cancels the offset with a novel technique based on single or double chopping. The(More)
— An ultra low-power SAR ADC is presented. The circuit is the interleaved version of an already designed SAR converter with improved performance. This design uses 7 interleaved converters and achieves a conversion rate of 700 kS/s. The converter has been simulated by using a 0.18-m CMOS technology showing a power consumption as low as 40 W which allows(More)
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