Andrés Takach

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THE GROWING CAPABILITIES of silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to move to higher abstraction levels. Raising the abstraction levels and accelerating automation of both the synthesis and the verification processes have for this reason always been key factors in the(More)
The ever-increasing chip power dissipation in SoCs has imposed great challenges on today’s circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations are performed under deterministic conditions. With the(More)
The Princeton University Behavioral Synthesis System (PUBSS) is a high-level synthesis system targeted to control-dominated machines. PUBSS accepts a VHDL subset, in which the design can be described as multiple communicating processes plus registers, and generates a register-transfer implementation. This paper describes the compiler wi(h emphasis on the(More)
DESIGN COMPLEXITY is continually rising with the higher levels of integration implied by Moore’s law. Functional complexity increases with our ability to incorporate more computation in SoCs and to create more complex applications. Additional complexity is also introduced in the design process by the need to control power consumption and to tackle(More)
This paper describes a new algorithm for generation of scheduling constraints in networks of communicating processes. Our model of communication intertwines the schedules of the machines in the network: timing constraints of a machine may aaect the schedules of machines communicating with it. This model of communication facilitates the modular speciication(More)
As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, <i>worst-case</i> timing analysis may lead to overly conservative synthesis, and may end up using excess resources to guarantee design constraints. In this paper, we propose an(More)
The algorithms used in wireless applications are increasingly more sophisticated and consequently more challenging to implement in hardware. Traditional design flows require developing the micro architecture, coding the RTL, and verifying the generated RTL against the original functional C or MATLAB specification. This paper describes a C-based design flow(More)
Aging effects (such as Negative Bias Temperature Instability (NBTI)) can cause the temporal degradation of threshold voltage of transistors, and have become major reliability concerns for deep-submicron (DSM) designs. Meanwhile, leakage power dissipation becomes dominant in total power as technology scales. While multi-threshold voltage assignment has been(More)