André Klindworth

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This paper investigates the implementation of computations over nite elds GF(2 m) using eld-programmable logic devices (FPLDs). Implementation details for addition/subtraction, multiplication , square, inversion, and division are given with mapping results for Xilinx LCAs, Altera CPLDs and Actel ACT FPGAs. As an application example, mapping results for(More)
This paper presents a tool-set for simulating Altera-PLDs 1] using VHDL 2]. It has been successfully used in a graduate course on digital design with PLDs. The tool-set supports timing simulation as well as functional simulation of designs that have been designed with the Altera MAX+plusII development tool. 1 Background Altera's PLD/FPGA design tool(More)
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