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As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express ® , DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be(More)
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