Learn More
This paper presents a microscopic traffic simulation-based method for urban traffic state estimation using Assisted Global Positioning System (A-GPS) mobile phones. In this approach, real-time location data are collected by A-GPS mobile phones to track vehicles traveling on urban roads. In addition, tracking data obtained from individual mobile probes are(More)
Increasing smartphone penetration, combined with the wide coverage of cellular infrastructures, renders smartphone-based traffic information systems (TISs) an attractive option. The main purpose of such systems is to alleviate traffic congestion that exists in every major city. Nevertheless, to reap the benefits of smartphone-based TISs, we need to ensure(More)
This paper proposes a novel evolutionary approach based on a modified Imperialist Competitive Algorithm for analog circuit design optimization. The original Imperialist Competitive Algorithm shows a low search ability in high-dimensional search spaces which is the case in optimization of analog circuits. The proposed tool addresses this problem by(More)
This paper presents the design methodology and underlying algorithms of a tool developed for automated receiver design and optimization for fourth generation (4G) wireless communication systems. An algorithm to systematically design and optimize the receiver budget for the multi-standard case is introduced. The goal of this algorithm is to find a(More)
In this paper, the use of continuous-time implementation in extended-range (ER) incremental sigma-delta analogto-digital converters is analyzed in order to explore a possible solution to low-power multichannel applications. The operation principle, possible loop filter topologies, and critical issues are considered using a general approach. It is(More)
The performance of continuous-time (CT) sigmadelta (ΣΔ) modulators is severely degraded by the clock jitter induced timing variation in their feedback digital-to-analog converters (DACs). To mitigate this non-ideality, jitter sensitivity reduction techniques that employ exponentially decaying pulse shape DACs have been recently reported. In this paper,(More)
This paper presents a sigma-delta modulator architecture with improved linearity over a frequency band from DC to 10MHz. The proposed modulator architecture employs the 2nd order 4-bit sigma-delta modulator with feedforward signal path in a 2-2 modified cascaded configuration, which greatly improves the tonal behavior even at 8X oversampling ratio (OSR). A(More)