Ana Cristina M. Pinto

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This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high(More)
The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. Electric-level simulation is more accurate but may not be applied to large combinational blocks due to thelong execution time to simulate all possible input situations. A possible(More)
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