• Citations Per Year
Learn More
Bang-Bang Phase Locked Loops (BB-PLLs) exhibit a nonlinear response that is dependent on the magnitude of the phase error. This paper presents a novel Digital Loop Filter (DLF) with coefficients that adapt to the relative magnitude of the phase error, and hence, enhances system linearity. An All-Digital BB-PLL (BB-ADPLL) that incorporates the proposed DLF(More)
Bang-Bang phase locked loops (BB-PLLs) offer a low power implementation of digital PLLs. However, the response of BB-PLLs, unlike linear PLLs, depends on the magnitude of the phase error, and thus, exhibits hard nonlinearity. This paper presents a generic modeling methodology for digital BB-PLLs in the locked state using simple time domain analysis. The(More)
This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The proposed model exploits the sampled nature of the PLL where most of its analog behavior takes effect during the phase detection, and remains almost constant during the rest of the reference cycle. The PLL(More)
In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all(More)
  • 1