Amit Prakash

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We present new results and numerical studies of very fast schedulers for SMS (Switch-Memory-Switch) routers, which emulate output-queuing by buffering packets in a partitioned shared-memory located between input and output ports. The architecture of Juniper’s core routers and Brocade’s storage switches is based on SMS. Our numerical results demonstrate that(More)
We present a simple and near optimal randomized parallel scheduling algorithm for scheduling packets in routers based on the <i>Switch-Memory-Switch</i> (<i>SMS</i>)architecture, which emulates 'output queuing' by using a collection of small memories within the switch to buffer packets, and which forms the basis of the fastest routers in use today. For a(More)
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardware implementation of a Low Density Parity Check code (LDPC) indicates that interconnect complexity dominates the VLSI cost. We describe a heuristic interconnect-aware synthesis(More)
This paper presents the details of the system we prepare as a participant of the PAN 2014 task on 'Source Retrieval: Uncovering Plagiarism, Authorship, and Social Software Misuse'. Our work is focused on intelligent chunking of suspicious documents and a hybrid approach of query formation. A method based on term frequency and word co-occurrence is proposed(More)
PURPOSE OF REVIEW Clinical and experimental data suggest that hypergylcaemia lowers the ischaemic neuronal threshold and worsens outcome in the presence of neurological injury from trauma, stroke and subarachnoid haemorrhage. This review aims to appraise the evidence for tight glycaemic control in patients with neurological injury. RECENT FINDINGS(More)