Amit Chowdhary

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In majority of high-performance custom IC designs, designers take advantage of the high degree of regularity present in circuits to generate e cient layouts in terms area and performance as well as to reduce the design e ort. In this paper, we explain how regularity manifests itself at functional, structural and topological levels. Using these notions, we(More)
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate optimization requires timing information from a signoff static timing analyzer, we propose an incremental placement algorithm that uses timing information from a signoff static(More)
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first force directed placement algorithm that meets precise half perimeter bounding box constraints on critical nets. It builds on the work of Eisenmann et al. [12], adding a new net(More)
We show that the FPGA technology mapping problem can be efficiently implemented as a mixed integer linear programming (MILP) problem which generates truly optimal mappings. The MILP approach can handle a wide variety of FPGA logic block architectures. We present a compact MILP formulation for logic blocks based on lookup tables (LUTs) multiplexers. We also(More)
tioned into data path and control blocks. The data path block performs Boolean (AND, OR, XOR) or arithmetic (ADD, SHIFT, MULTIPLY) operations on data and address buses. Control logic generates signals that control the data path’s operation. Control logic is usually very random, whereas data path logic is highly regular because it performs similar operations(More)