Amir Mahdi Hosseini Monazzah

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ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM(More)
Nowadays, leakage energy constitutes up to80% of total cache energy consumption and tag array isresponsible for a considerable fraction of static energyconsumption. An approach to reduce static energyconsumption is to replace SRAMs by STT-RAMs with nearzero leakage power. However, a problem of an STT-RAMcell is its limited write endurance. In spite of(More)
Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However,(More)
In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only(More)
Emerging STT-MRAM memories are promising alternatives for SRAM memories to tackle their low density and high static power consumption, but impose high energy consumption for reliable read/write operations. However, absolute data integrity is not required for many approximate computing applications, allowing energy savings with minimal quality loss. This(More)
With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to(More)
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