Amir Hirsch

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This paper presents the J Computer, a processor that natively implements a subset of the Java Virtual Machine specification for Java ME CLDC v1.0a in hardware. The computer contains a 32-bit microprocessor, method code cache, and a number of hardware device modules, such as a tone generator, a PS/2 keyboard, and an alpha-blending VGA graphics renderer into(More)
The main challenge in the VLSI design of an efficient JPEG2000 hardware is the block coder (BC) engine for the embedded block coding with optimised truncation (EBCOT). In this paper, we present the VLSI design of a BC system that can process 21 mega pixels per second. For the bit plane coder (BPC), we employ a concurrent symbol processing (CSP) algorithm to(More)
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