Learn More
| In this paper we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned oo by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are(More)
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clocked elements. We propose a method of obtaining the switching activity patterns of the clocked(More)
Sleep mode operation and exploiting it to minimize the average power consumption are o f g r e at importance. In this paper, we formulate the memory segmentation/partitioning problem to exploit sleep mode operation and show that the problem is NP-complete. We present polynomial time algorithms for special classes of the problem. Some generalizations of the(More)
In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power, and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning , estimation, analysis, and optimization. Key design quality metrics from(More)
For a set S of intervals, the clique-interval I S is deened as the interval obtained from the intersection of all the intervals in S , and the clique-width quantity w S is deened as the length of I S. Given a set S of intervals, it is straightforward to compute its clique-interval and clique-width. In this paper we study the problem of partitioning a set of(More)