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- Amir H. Farrahi, Majid Sarrafzadeh
- IEEE Trans. on CAD of Integrated Circuits and…
- 1994

- Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
- IEEE Trans. on CAD of Integrated Circuits and…
- 2001

In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are… (More)

- Amir H. Farrahi, Majid Sarrafzadeh
- FPL
- 1994

- Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh
- ICCAD
- 1995

In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle times of the clocked elements. We propose a method of obtaining the switching activity patterns of the clocked… (More)

- Amir H. Farrahi, Savita A. Verma
- 29th Digital Avionics Systems Conference
- 2010

To facilitate pairing of aircraft while meeting a schedule, the pair-scheduling problem for landing aircraft in Very Closely Spaced Parallel Approaches was studied. An earlier prototype was adopted and the scheduling algorithm was extended in several ways to improve the solution quality and expand the range of constraints it could handle. This paper… (More)

Sleep mode and exploiting it to maximize sleep time are of great importance in low power synthesis of digital circuits. The motivation is to de-activate the memory refresh circuitry, apply power down or just disable the clock signals during the inactive periods of operation of circuit elements, and thus minimize the power consumption. Since it is… (More)

- Amir H. Farrahi, Majid Sarrafzadeh
- ICCAD
- 1995

Abstract: Partitioning of a system to maximize exploitable sleep time for low-power synthesis is discussed. The motivation is to deactivate the memory refresh circuitry, apply power down or disable the clock signals during the inactive periods of operation of circuit elements, and thus minimize the power consumption. Since it is impractical to have a… (More)

In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power, and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a… (More)

- Amir H. Farrahi, Gustavo E. T ellez, Majid Sarrafzadeh
- 2001

Sleep mode operation and exploiting it to minimize the average power consumption are of great importance in modern VLSI circuits. In general, sleep mode refers to the mode in which part(s) of the system are idle. In this paper, we study the problem of partitioning a circuit according to the activity patterns of its elements such that circuit elements with… (More)

- Amir H. Farrahi, D. T. Lee, Majid Sarrafzadeh
- Algorithmica
- 1999

For a set S of intervals, the clique-interva I S is defined as the interval obtained from the intersection of all the intervals in S , and the clique-width quantity w S is defined as the length of I S . Given a set S of intervals, it is straightforward to compute its clique-interval and clique-width. In this paper we study the problem of partitioning a set… (More)