Amin Ojani

  • Citations Per Year
Learn More
Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the outof-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay(More)
In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the stringent requirements on the amplifier to be(More)
Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by(More)
This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during(More)
This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO(More)
Time-interleaved ∆Σ (TIDSM) DACs have the potential for a wideband operation. The performance of a twochannel interleaved ∆Σ DAC is very sensitive to the duty-cycle of the half-rate clock. This paper presents a closed-form expression for the SNDR loss of such DACs due to duty cycle error for modulators with a noise transfer function of (1 − z−1). Adding a(More)
  • 1