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©2014 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Abstract—Periodic(More)
Cover image: The cover image illustrates a sine-shaped " wordle " of the thesis. Abstract Ever increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed(More)
This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO(More)
—Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined(More)
In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the stringent requirements on the amplifier to be(More)
This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during(More)