Amin Khajeh Djahromi

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This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on(More)
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a(More)
Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. We present Multi-Copy Cache (MC<sup>2</sup>), a new(More)
This paper presents a single, scalable, unified statistical model that accurately reflects the impact of random embedded memory failures due to power management policies on the overall performance of a communication system. The proposed framework enables system designers to efficiently and accurately determine the effectiveness of novel power management(More)
As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling(More)
The universal underlying assumption made today is that systems on chip must maintain 100% correctness regardless of the application. This work advocates the concept that some applications - by construction - are inherently error tolerant and therefore do not require this strict bound of 100% correctness. In such cases, it is possible to exploit this(More)
This paper discusses how the cognitive radio concept can be extended to allow the system not only to manage shared resources such as spectrum, but to use this knowledge to optimize the overall system power consumption. We introduce a case study of video over wireless via a 3G WCDMA modem connected to an H.264 decoder. We show that by utilizing knowledge(More)
Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage <i>V</i><sub><i>dd</i></sub> and temperature on memory performance and their interrelationships. We propose a(More)