Ameya Patil

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It is well-known that the precision of data, hyperparameters, and internal representations employed in learning systems directly impacts their energy, throughput, and latency. The precision requirements for the training algorithm are also important for systems that learn on-the-fly. Prior work has shown that the data and hyperparameters can be quantized(More)
A variety of vision ailments are indicated by structural changes in the retinal substructures of the posterior segment of the eye. In particular, integrity of the inner-segment/outer-segment (IS/OS) junction directly relates to the visual acuity. In the en-face optical coherence tomography (OCT) image, IS/OS damage manifests as a dark spot in the foveal(More)
This paper describes a multi-functional deep in-memory processor for inference applications. Deep inmemory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings(More)
Ameya Patil1, Naresh Shanbhag1, Lav Varshney1, Eric Pop2, H.-S. Philip Wong2, Subhasish Mitra2, Jan Rabaey3, Jeffrey Weldon4, Larry Pileggi4, Sasikanth Manipatruni5, Dmitri Nikonov5, and Ian Young5 1Univ. of Illinois at Urbana-Champaign, IL, 2Stanford Univ., Stanford, CA, 3Univ. of California, Berkeley, CA, 4Carnegie Mellon Univ., Pittsburgh, PA, 5Intel(More)
Emerging applications require computing platforms to extract task-relevant information from increasingly large amounts of data. These requirements place stringent constraints on energy efficiency, throughput, latency, and for certain data types, security and privacy of computing platforms. Traditionally, silicon CMOS scaling has been relied upon to meet(More)
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