Aman Aflaki

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Time-domain channel characterization (TCC) for de-embedding of an asymmetric fixture is introduced. Two design criteria for the design of a 2x-thru are proposed. Error sensitivity regarding a small error in the S-parameters of the 1x-fixture is analyzed with an insertion loss error-coefficient and a return loss error-coefficient. The TCC procedure,(More)
As DDR speed continues to increase, uncorrelated timing jitter becomes a significant portion of channel timing budget. The dominant component of uncorrelated timing jitter comes from power supply noise induced jitter (PSIJ). DDR systems rely on tracking of this jitter between data and strobe signals. Due to inherent 90 degree offset between data and strobe(More)
External loopback testing is an industry standard test for serializer-deserializer (SERDES) interfaces, and it is used to test for at-speed defects in the analog transmission (TX) and reception (RX) buffers. The specific test involves sending pseudorandom bit sequence (PRBS) at high speed from the TX side, looping on the load-board and receiving on the RX(More)
Jitter behavior has become increasingly critical design considerations for 12Gbps and 28Gbps transceiver devices featuring stringent specification compliance. In this paper, we present a comprehensive study of noise to jitter transfer mechanism, in which two dominant yet distinct jitter causes, power supply noise and signal crosstalk are investigated by(More)
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