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The building block of a Network-on-Chip (NoCs) is its router. It is responsible to switch the channels which forward the messages exchanged by the cores attached to the NoC, and the costs and performance of the NoC strongly depends on the router architecture. In this paper, we present RASoC, a router architecture intended to be used in the building of low(More)
Networks-on-chip (NoCs) are communication architecture alternatives for complex Systems-on-Chip (SoCs) designs, due to their high scalability and bandwidth. In this paper, we consider a heterogeneous NoC as an alternative to match performance and energy requirements for dedicated applications. By employing an optimized mix of different routers, a(More)
Networks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in Systems-on-Chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose architecture has great impact on the costs and on the performance of the network. This work presents a(More)
In this study we investigated event related-potential (ERP) component c247, which reflects the recognition process in two classes of subject: a sample with high risk (HR) for alcoholism and a sample of control subjects with low risk (LR). The results of this study suggest that the amplitude of the c247 to repeated pictures of common objects was decreased(More)
In this work, a correlation between Event Related Potential (ERP) and visual memory, generally located in occipito-temporal region was found for two classes of subject: a sample with high risk (HR) for alcoholism and a sample of control subjects with low risk (LR). For the ERPs of matching stimulus we describe an application of an artificial neural network(More)