Alireza Tajary

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High defect density and extreme process variation for nanoscale self-assembled crossbar-based architectures have been expected to be as fundamental design challenges. Consequently, defect and variation issues must be considered on logic mapping on nanoscale crossbars. In this paper, we investigate a greedy algorithm for the variation and defect aware logic(More)
In this paper, a throughput-aware transient fault detection method is presented with respect to the features of server processors. The proposed method takes the advantages of combination of reconfigurable redundant execution-based fault detection and speculative fault detection. The reconfigurable redundant execution-based fault detection method by using(More)
Article history: Received 17 October 2015 Received in revised form 3 February 2016 Accepted 23 March 2016 Available online xxxx In this paper, a method to mitigate silent data corruptions (SDCs) is proposed. This paper, first, shows and characterizes instruction result locality based on several simulation results and next, proposes an architecture called(More)
This paper proposes: 1) A dynamically scheduled Process-Level Redundancy (PLR) for enhancing reliability of multi-core systems, 2) A comparison between PLR and Thread-Level Redundancy (TLR), and 3) A fault study on the thread selector unit of a modern processor. The proposed technique employs underutilized CPU resources to improve fault tolerance ability of(More)
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