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The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In(More)
—This paper presents a topology for Gilbert-cell mixer that leads to a better performance in terms of noise figure, conversion gain and IIP3 at low supply voltage. In this architecture, we have used an extra LC filter for reduction parasitic capacitance noise in switching. Simulation results show the voltage CG of 17.45 dB, NF of 7.04 dB, and IIP3 of-4 dBm.
— A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an(More)
In this paper a Low power divide-by-two static frequency divider using GDI D flip-flop is proposed which uses only single clock phase. So, the timing problem of complementary clock signals is relaxed. This divider is simulated in a standard 0.18µm CMOS process. Simulation results indicate that the proposed divider consumes, in the worst case, 3.74mW(More)