Ali Shahabi

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As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to develop techniques for reusing faulty dies, even with a degraded performance. In this paper, a new method for high level synthesis of degradable ASICs is presented. Our technique(More)
The decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of NoC-based design techniques, has necessitated the search for network reconfiguration techniques for reusing NoCs with faulty components. In this paper, we propose a new method to cope with the problem of faulty(More)
The decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of NoC-based design techniques, has necessitated the search for network reconfiguration techniques for reusing NoCs with faulty communication hardware. In this paper, we propose a method to cope with the problem of faulty(More)
Online testing, one of the most challenging issues in design for test domain, is intended for inspection of digital systems behavior during their working period. This paper presents a novel approach for simultaneous online testing of several combinational circuits using a reconfigurable neural network implemented along the original hardware. Automatic(More)
The decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of NoC-based design techniques, has necessitated the search for network reconfiguration techniques for reusing NoCs with faulty communication hardware. In this paper, we propose a method to cope with the problem of faulty(More)
The decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of 3D-NoC based design architectures, has necessitated the search for network reconfiguration techniques in order to make faulty networks reusable. In this paper, we first introduce an efficient and scalable hardware(More)
Matrix multiplication is an important basic operation that is used in a vast range of applications like image processing and DSP. The design and implementation of a new matrix multiplication module is the main focus of this paper. Our proposed matrix multiplier hardware can easily be re-configured in order to accept any pair of input matrices that are(More)
Two of the most challenging issues in online testing are deriving a general tester scheme for various circuits and reducing the area overhead. This paper presents a novel reconfigurable online tester using artificial neural networks to test combinational hardware. Our proposed BIST architecture has the capability of testing a number of arbitrary sub-modules(More)
This paper describes a procedure for estimating the parasitic impedances associated with multi-chip power module (MCPM) interconnections and packaging at finer granularity than has been previously demonstrated. The methodology introduced here makes it possible to determine an estimate for the loop inductance at each individual semiconductor die position(More)
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