Ali Ahaitouf

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This paper presents an efficient VLSI architecture of a high speed, low power 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast lifting scheme approach for (9, 7) filter in DWT, reduces the hardware complexity and memory accesses. Moreover, it has the ability of performing progressive computations by minimizing the(More)
A Variable Node Processing Unit (VNPU) and a Check Node Processing Unit (CNPU) are designed in order to be used in Low Density Parity Check (LDPC) decoding by the Min-Sum Algorithm (MSA). The designed blocks are fully parallel and flexible to be used for different block length when a regular (3, 6) LDPC codes are required. The proposed VNPU and CNPU have(More)
Embedded block coding with optimized truncation (EBCOT) is an important feature of the latest digital still-image compression standard, JPEG2000; however, it consumes more than 50% of the computation time in the compression process. In this paper, we propose a new high speed VLSI implementation of the EBCOT algorithm. The main concept of the proposed(More)
We propose a novel adaptation of the Ant Colony Optimization (ACO) Technique to optimize analog circuits sizing and design. The proposed algorithm is first tested and its performances are highlighted by using some mathematical test functions. This new adaptation of the ACO algorithm is then directly applied to optimize the design of typical analog circuits,(More)
— In this paper, a decoding technique for the concatenated codes based on the Bose-Chaudhuri-Hocquenghem code (BCH) and the low density parity check (LDPC) is proposed. It is based on the berlekamp-massey and sum-product algorithms. The output values delivered by the sum-product algorithm, after a fixed number of iterations, are used as input values to(More)
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