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In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of(More)
In this paper, a new approach for reducing the subthreshold leakage current of digital circuits is proposed. It does not use a multi-threshold process technique which is more expensive. The technique which makes to use of a new variable supply voltage oscillator, combines the ideas of both Standby Leakage Control Using Transistor Stacks (SRB) and variable(More)
—In this paper, we propose a technique for custom instruction (CI) extension considering process variations. It bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In the proposed method, instead of using the conventional static timing analysis (STA), statistical static timing analysis (SSTA) which(More)
Keywords: Network-on-chip Routing algorithm Adaptive Dynamic XY Bursty traffic Non uniform traffic Low latency routing Link failure tolerant a b s t r a c t In this paper, an adaptive routing algorithm for two-dimensional mesh network-on-chips (NoCs) is presented. The algorithm, which is based on Dynamic XY (DyXY), is called Enhanced Dynamic XY (EDXY). It(More)
— This paper mixes two encoding techniques to reduce test data volume, test pattern delivery time and power dissipation in scan test applications. This is achieved by using the Run-Length (RL) encoding followed by Huffman encoding. This combination is especially effective when the ratio of don't cares in a test set is high which is a common case in today's(More)
— In this paper, an optimal approach for the design of 6-T FinFET based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of Particle(More)
In this work, first an accurate model for I-V characteristics of sub-90-nm MOSFET in the linear and saturation regions is proposed. The model, which is intended for fast analytical calculation of the current, is based on the BSIM3v3 model. Instead of using constant V th and V A voltages, as is assumed in the BSIM3v3 model, these voltages are defined as(More)
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in future technologies the static portion of power dissipation will outreach the dynamic portion. This paper proposes an efficient technique to reduce both dynamic and static power(More)