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In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of(More)
— As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we present a set of data encoding schemes aimed at reducing the power dissipated by the links of an NoC.(More)
— In this paper, an optimal approach for the design of 6-T FinFET based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of Particle(More)
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock synchronization, replication, or barrier synchronization. Among several multicast schemes proposed in on chip interconnection networks, path-based multicast scheme has been proven to(More)
A novel time borrowing method called dynamic Flip-Flop conversion is presented in this paper. A timing violation predictor detects the violations halfway in the critical path and dynamically converts the critical Flip-Flop to a latch. This way, time borrowing benefits of latches are utilized in a Flip-Flop based design which is more adaptable with(More)
Keywords: SRAM Dynamic back-gate design FinFET Robust Low power a b s t r a c t In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this(More)
—This paper proposes a technique for dynamic power reduction of pipelined processors. It is based on eliminating unnecessary transitions that are generated during the execution of NOP instructions. The approach includes the elimination of unnecessary changes in pipe register contents and the limitation of boundary movement of transitions caused by(More)