Alfio Zanchi

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The ADC presented demonstrates the efficiency of the straight 1.5 bit-per-stage pipelined approach up to 12b resolution and 80MSps speed. Performance of 66dB SNR and 75dB SFDR at 80MSps/31MHz input is obtained without calibration, drawing 192mW in the analog core (259mW total) from 3V supply. Same values are achieved at 100MSps when the power is increased(More)
The advent of modern-day wireless communications systems as well as other high speed applications imposes exceedingly challenging demands on state-of-the-art Analog-to-Digital Converters (ADCs). The evolution of receiver architectures necessitates very high Signal-to-Noise Ratio (SNR) at intermediate frequencies that up until recently were impossible to(More)
This work introduces design techniques and experimental results relative to a 16b 65MSps pipeline ADC core implemented in 0.4/spl mu/m, 45GHz-fr SiGe BiCMOS. A fast methodology for simulating the INL with Spice enables the implementation of low-distortion sample/hold and quantizer at 3.3V supply and high input range (4Vpp). Accurate prediction of aperture(More)
A Radiation-Hardened By Design 8-bit 32nm SOI CMOS pipeline ADC shows no AC performance nor non-linearity worsening vs. TID when operated at 200MSps sampling rate, -1dBFS sinewave input amplitude. The circuit shows no visible performance variation during irradiation, and maintains >42dBFS SNR, >61dBc SFDR up to 1Mrad(Si) after LMS (Least(More)
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