Learn More
This work introduces design techniques and experimental results relative to a 16b 65MSps pipeline ADC core implemented in 0.4/spl mu/m, 45GHz-fr SiGe BiCMOS. A fast methodology for simulating the INL with Spice enables the implementation of low-distortion sample/hold and quantizer at 3.3V supply and high input range (4Vpp). Accurate prediction of aperture(More)
The advent of modern-day wireless communications systems as well as other high speed applications imposes exceedingly challenging demands on state-of-the-art Analog-to-Digital Converters (ADCs). The evolution of receiver architectures necessitates very high Signal-to-Noise Ratio (SNR) at intermediate frequencies that up until recently were impossible to(More)
  • 1