Alexis Farcy

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Through Silicon Via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more(More)
EUROSERVER is a collaborative project that aims to dramatically improve data centre energy-efficiency, cost, and software efficiency. It is addressing these important challenges through the coordinated application of several key recent innovations: 64-bit ARM cores, 3D heterogeneous silicon-on-silicon integration, and fully-depleted silicon-on-insulator (FD(More)
A TCAD-based simulation approach is proposed to study the impact of transient coupling that occurs within a generic 3D integration on 65 nm technology based CMOS devices. This coupling is mainly due to signals applied on redistribution layer (RDL) and through-silicon vias (TSV). These both 3D-inherent metal structures may cause variations on normal(More)
3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customer’s interest by showing him(More)
Wafer level molding is an important process step in the chip on wafer approach and seems currently required in stacking first process flow. Thermo-mechanical properties of molding material has to be controlled to limit stress induce by CTE mismatch with silicon wafer and also to assure planarization and protection functions. 2D and 3D finite element(More)