Alexey Petrovsky

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In this paper we investigate a small broadside planar (2D) su-perdirective microphone array for speech acquisition in the car and compare its performance to linear arrays. The objective of this investigation is to replace an expensive directional microphone by a small array of inexpensive omnidirectional sensors. Since the array was designed to be used in(More)
The paper considers techniques for grouping objects that are described with many quantitative and qualitative attributes and may exist in several copies. Such multi-attribute objects may be represented as multisets or sets with repeating elements. Multiset characteristics and operations under an arbitrary number of multisets are determined. The various(More)
This paper considers the technique to construct the general decision rule for the contradictory expert classification of objects which are described with many qualitative attributes. This approach is based on the theory of multiset metric spaces, and allows to classify a collection of multi-attribute objects and define the classification rule which(More)
In this paper, dynamic algorithm transforms (DAT) for re-configurable real-time processor for audio application based on the adaptive wavelet packet (WP) decomposition are presented. DAT techniques is to constrain a minimum cost sub-band decomposition of wavelet transform by maxi-minimizing the minimum masking threshold (which is limited by the perceptual(More)
This paper presents two fundamental enhancements in a hybrid audio/speech signal model based on AM/FM and transient representation: sinusoidal, transient, and noise (STN) components. The first enhancement involves a method of instantaneous sinusoidal parameters estimation using an adaptive filtering of the speech signal along its harmonic components. The(More)
—The paper reports on an attempt to implement a real-time hardware H.264 video decoder. The initial results of the project are presented, especially a customized RISC core and some digital modules, both of which have been implemented in Xilinx FPGA. The former has to serve as a host processor that supervises the latter, which speed up the essential decoding(More)