Alexey Lopich

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In this paper we present a vision processor, which incorporates a 160&#x00D7;80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm<sup>2</sup> and is fabricated in a standard 0.18 &#x03BC;m CMOS process. The I/O(More)
This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SIMD processor array. The proposed(More)
In this paper we present an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low power consumption. A 24 times 60 proof-of-concept array integrated(More)
In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits from full programmability (discrete-time mode) and high operational performance in global image processing operations (continuous-time mode) thus extending the application field of(More)
A vision chip operating with 1.9pJ/OP efficiency has been fabricated in 0.18μm CMOS. Each of the 256x256 pixel-processors (dimensions 32x32μm), contains 14 binary and 7 analog S2I registers coupled to a photodiode, an arithmetic logic unit, diffusion and asynchronous propagation networks. At the chip’s periphery, facilities exist to allow pixel address(More)
This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit(More)
We present a new approach to execution of global image processing operations on massively parallel cellular processor arrays. Combining conventional synchronous processing with simple asynchronous propagations we achieve performance increase on global operations without additional hardware cost. By the example of watershed transformation we demonstrate the(More)
In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) – a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are(More)