Alexey Lopich

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— In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) – a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are(More)
— In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pixel-processors. The processor operates with a 100MHz clock and 1.8V supply. The device provides 640 GOPS (binary) and 23 GOPS (greyscale) consuming 0.5 W. The chip occupies 50mm 2 and is fabricated in a standard 0.18 μm CMOS process. The I/O interface supports 200(More)
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete-and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SIMD processor array. The proposed(More)
A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in O.1811m CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also(More)
In this work we present a design of a massively­ parallel cellular processor array implemented in 3D CMOS technology. The proof of concept 128x96 array device is partitioned across two custom designed layers. Additionally, three layers of DDR memory are vertically stacked and bonded underneath. The processor benefits from 358Gbit/s data rate between memory(More)
— A demonstration is made of the high-speed real-time image processing capabilities of the SCAMP-5 vision chip. The device provides a software-programmable 256x256 pixel-parallel SIMD processor array. In the example application, the IC can determine dimensions and the location of a single object, at a sustained rate of 100,000fps. At 30,000fps, the chip can(More)
— A prototype vision chip has been designed that incorporates a 20 x 64 array of processing elements on a 31μm pitch. Each processor element includes 14 bits of digital memory in addition to 7 analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells(More)