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— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete-and continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SIMD processor array. The proposed(More)
A vision chip operating with 1.9pJ/OP efficiency has been fabricated in 0.18μm CMOS. Each of the 256x256 pixel-processors (dimensions 32x32μm), contains 14 binary and 7 analog S2I registers coupled to a photodiode, an arithmetic logic unit, diffusion and asynchronous propagation networks. At the chip's periphery, facilities exist to allow pixel address(More)
— In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) – a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are(More)
In this paper we present an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low power consumption. A 24 times 60 proof-of-concept array integrated(More)
This paper presents a design and implementation of an application specific cellular processor array (CPA) that executes binary image skeletonization on a hexagonal lattice. The designed CPA operates in an asynchronous mode, employing 'pixel per processor' concept, which provides significant performance increase in image processing operations that exploit(More)
This paper presents the design of a vertically-integrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype 'vision chip' contains a 32¥32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode(More)
A combined analogue and digital processing element for a pixel-parallel vision chip has been designed in O.1811m CMOS technology. In addition to 7 analogue registers, each pixel incorporates 14 bits of digital memory. In the analogue domain its processing capabilities include addition, subtraction and squaring, with digital domain NOT and OR operators also(More)