Learn More
Petri nets with read arcs are investigated with respect to their unfolding, where read arcs model reading without consuming, which is often more adequate than the destructive-read-and-rewrite modelled with loops in ordinary nets. The paper redeenes the concepts of a branching process and unfolding for nets with read arcs and proves that the set of reachable(More)
In this tutorial paper we survey some of the existing techniques for modelling, analysis and synthesis of asynchronous control circuits. All these methods are based on the use of Petri nets as a tool for describing the behaviour of such circuits. The descriptive power of Petri nets allows them to model a wide range of asynchronous circuit components,(More)
| This paper describes a novel approach t o timing analysis and verication of asynchronous circuits with bounded delays. The method is based on the time-driven unfolding of a time Petri net model of a circuit. Each reachable state, together with its timing constraints is represented implicitly. Our method is used to verify freedom from hazards in(More)
This paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the form of the STG-unfolding segment to derive the logic implementation using approximation techniques. It is based on a new notion of slice, which localises the behaviour of a(More)
We describe a technique for the design and analysis of a simple asynchronous microprocessor from a Labelled Petri Net speciication. The implementation is obtained by means of reenement, transformation and translation. Several versions of the microprocessor design are presented, evaluated and compared. The Petri net based approach allows an interplay of(More)
This paper presents a novel technique for synthesis of speed-independentcircuits. It is based on partial order representation ofthe state graph called STG-unfolding segment. The new methoduses approximation technique to speed up the synthesis process.The method is illustrated on the basic implementation architecture.Experimental results demonstrating its(More)