Alexander T. Ishii

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AMD’s 32-nm x86-64 core code-named “Piledriver” features a resonant global clock distribution to reduce clock distribution power while maintaining a low clock skew. To support a wide range of operating frequencies expected of the core, the global clock system operates in two modes: a resonant-clock (rclk) mode for energy-efficient operation over a desired(More)
Multilayer routing is an important problem in the physical design of integrated circuits as technology evolves towards several layers of metallization. MulCh is a channel router accepting specification of an arbitrary number of routing layers. Though several other channel routers for three layers of interconnect have been proposed, the only previously(More)
We investigate two strategies for reducing the clock period of a two-phase, level-clocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edge-triggered latches into a faster level-clocked one. We model a two-phase circuit as a graph(More)
In this paper we present a polynomial-time algorithm for pipelining two-phase, level-clocked circuits in order to operate correctly with a given clocking scheme under the bounded delay model. In this model, the propagation delay of each combinational logic element v is assumed to have a minimum value (v) and a maximum value d(v). Our algorithm runs in O(LV(More)
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