Alexander T. Ishii

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We investigate two strategies for reducing the clock period of a two-phase, level-clocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edge-triggered latches into a faster level-clocked one. We model a two-phase circuit as a graph(More)
AMD's 4+ GHz x86-64 core code-named " Piledriver " employs resonant clocking [1,2,3,4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk)(More)
In this paper we present a polynomial-time algorithm for pipelining two-phase, level-clocked circuits in order to operate correctly with a given clocking scheme under the bounded delay model. In this model, the propagation delay of each combinational logic element v is assumed to have a minimum value (v) and a maximum value d(v). Our algorithm runs in O(LV(More)
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