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—Verification has long been recognized as an integral part of the hardware design process. When designing a system, engineers usually use various design representations and concretize them step by step up to a physical layout. At the beginning of the process, when there is much of indeterminacy, only abstract reference models are applicable to verification;(More)
Automatic generation and simulation of test programs is known to be the main means for verifying microprocessors. The problem is that test program generators for new designs are often developed from scratch with little reuse of well-tried components. State-of-the-art tools, like Genesys-Pro and RAVEN, meet the challenge by using a model-based approach,(More)
— Test program generation plays a major role in functional verification of microprocessors. Due to tremendous growth in complexity of modern designs and rigid constraints on time to market, it becomes an increasingly difficult task. In spite of powerful test program generators available in the market, development of functional tests is still known to be the(More)
—Functional testing of complex hardware and software systems has long been recognized as an immensely computer-intensive task. Consisting of a huge number of interacting components, computer systems are hard to be verified due to the well-known fundamental problem – combinatorial state explosion. One of the ways to overcome the complexity is to use abstract(More)
Runtime verification is checking whether a system execution satisfies or violates a given correctness property. A procedure that automatically, and typically on the fly, verifies conformance of the sys-tem's behavior to the specified property is called a monitor. Nowadays, a variety of formalisms are used to express properties on observed behavior of(More)
— In this paper an approach to testbench development for synchronous parallel-pipeline designs is considered. The approach is based on cycle-accurate formal specifications of a design under verification. Specifications include descriptions of control flow graphs of the design's operations and definitions of the microoperations with the help of Hoare(More)
Functional validation is a major bottleneck in hardware design. Two main approaches to ensure functional correctness of hardware systems are based on formal verification and simulation techniques. It is widely recognized that formal verification techniques are exhaustive but do not scale well; simulation-based techniques are scalable but are not exhaustive.(More)