Cascadable, CMOS synapse chips containing a cross-bar array of 32x32 (1024) programmable synapses have been fabricated as "building blocks" for fully parallel implementation of neural networks. Theâ€¦ (More)

The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics ofâ€¦ (More)

An electronic embodiment of a neural network based associative memory in the form of a binary connection matrix is described. The nature of false memory errors, their effect on the informationâ€¦ (More)

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of "long channel" NMOSFET binary connection elements implementedâ€¦ (More)

A novel thin film approach to neural network based high density associative memory is described. The information is stored locally in a memory matrix of passive, nonvolatile, binary connectionâ€¦ (More)

An electronic neural network for the Euclidean distance minimization problem, implemented in VLSI-based hardware, is described. The convergence properties of the neural-network hardware areâ€¦ (More)

This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardwareâ€¦ (More)