Learn More
—Reversible logic synthesis is an emerging research area to aid the circuit implementation for multiple nano-scale technologies with bounded fan-out. Due to the inherent complexity of this problem, several heuristics are proposed in the literature. Among those, reversible logic synthesis using decision diagrams offers an attractive solution due to its(More)
State-of-the-art techniques for enhancing system-level reliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability evaluation of the(More)
  • 1