Alessandro Gabrielli

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The paper explains the design and the realization of a small size high-speed fuzzy processor. The processor goal is to give more 3exibility to the front-end electronics for high-energy physics experiments. The chip can be applied as a general purpose data analyzer; particularly for analyzing and reducing on-line the data coming from detectors. The(More)
The industrial applications of fuzzy processors are increasing mainly in control and pattern recognition fields. Some of these applications require high speed that can not be obtained by standard commercial fuzzy processors. This paper describes the architecture of a very small size high speed fuzzy chip with two inputs and one output. The input sample rate(More)
In this paper we describe cost-time trade-off implementations of a triangular or trapezoidal membership function generator and of a no-contribute rule eliminator. In particular, as regards the membership function generator, two main solutions are described in details in order to meet the right user application. It is suggested to apply these solutions(More)
4 m’gger +tem in High Energv Physics Experiments (HEPEJ has to decide, in frw +s, if the data related to a nuclear event have to be stored or not. Normally. these data, are composed of a bit map where the track coordinates are stored. The possibiliv to use a suitable Fuzq Processor for HEPE has been investigated and the simulations show that a fast fi(More)
Alessandro Gabrielli, Enzo Gandolfi, Massimo Masetti Department of Physics, University of Bologna, via Irnerio 46,40126 Bologna Italy Phone: +39 51 630570 Fax +39-51-247244 E-mail: This paper describes the architecture of two VLSI Fuzzy chips designed to run at very high speed: 50 Mega Fuzzy Inference per Second (MFIPS) at least. The two(More)
Who is dealing with hardware architecture designs probably knows that in the past years many methodologies have been proposed and developed in order to increase the design feasibility. In more detail, many Hardware Description Languages (HDL) have become widespread overall for designing digital architecture from ever and ever highest design levels. In this(More)
This paper deals with two problems: the first concerns the design of the HW architecture of a high speed Fuzzy processor that can work at 50 Mega Fuzzy Inference per Second (MFIPS). It has eight 7 bit inputs and one 7 bit output. It is foreseen to apply it to a trigger device in HEP (High Energy Physics) experiments, the second one concerns the I pm CMOS(More)
The i.Drive Lab has developed inter-disciplinary methodology for the analysis and modelling of behavioral and physiological responses related to the interaction between driver, vehicle, infrastructure, and virtual environment. The present research outlines the development of a validation study for the combination of virtual and real-life research(More)