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We present \emph{Task Super scalar}, an abstraction of instruction-level out-of-order pipeline that operates at the task-level. Like ILP pipelines, which uncover parallelism in a sequential instruction stream, task super scalar uncovers task-level parallelism among tasks generated by a sequential thread. Utilizing intuitive programmer annotations of task(More)
Current and future parallel programming models need to be portable and efficient when moving to heterogeneous multi-core systems. OmpSs is a task-based programming model with dependency tracking and dynamic scheduling. This paper describes the OmpSs approach on scheduling dependent tasks onto the asymmetric cores of a heterogeneous system. The proposed(More)
It is widely accepted that future HPC systems will be limited by their power consumption. Current HPC systems are built from commodity server processors , designed over years to achieve maximum performance, with energy efficiency being an afterthought. In this paper we advocate a different approach: building HPC systems from low-power embedded and mobile(More)
Over the past few years, computer architecture research has moved towards execution-driven simulation, due to the inability of traces to capture timing-dependent thread execution interleaving. However, trace-driven simulation has many advantages over execution-driven that are being missed in multithreaded application simulations. We present a methodology to(More)
The performance of High Performance Computing (HPC) systems is already limited by their power consumption. The majority of top HPC systems today are built from commodity server components that were designed for maximizing the compute performance. The Mont-Blanc project aims at using low-power parts from the mobile domain for HPC. In this paper we present(More)
Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are they meant for this. Moreover, microarchitecture design decisions are(More)
The ability of Trametes villosa laccase, in conjuction with 1-hydroxybenzotriazole (HBT) as mediator and alkaline extraction, to remove lignin was demonstrated during treatment of wood (Eucalyptus globulus) and non-wood (Pennisetum purpureum) feedstocks. At 50 Ug(-1) laccase and 2.5% HBT concentration, 48% and 32% of the Eucalyptus and Pennisetum lignin(More)
As the number of transistors on a chip continues increasing the power consumption has become the most important constraint in processors design. Therefore, to increase performance , computer architects have decided to use multiprocessors. Moreover, recent studies have shown that heterogeneous chip multipro-cessors have greater potential than homogeneous(More)
Sampled simulation is a mature technique for reducing simulation time of single-threaded programs, but it is not directly applicable to simulation of multi-threaded architectures. Recent multi-threaded sampling techniques assume that the workload assigned to each thread does not change across multiple executions of a program. This assumption does not hold(More)
Eucalypt feedstock was pretreated with Myceliophthora thermophila laccase and methyl syringate, as mediator, in a multistage sequence consisting of successive enzymatic and alkaline peroxide stages, directly on the ground wood. Lignin modification was studied by two-dimensional (2D) nuclear magnetic resonance (NMR) of wood (at the gel state) after each(More)