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A new aggregated Hardware/Software (HW/SW) codesign approach to optimization of the digital signal processing techniques for enhanced imaging with real-world uncertain remote sensing (RS) data based on the concept of descriptive experiment design regularization (DEDR) is addressed. We consider the applications of the developed approach to typical(More)
Gaussian random numbers (GRN) generators are indispensable components in channel emulators for producing multiplicative and additive noises. Efficient designs of these GRN generators are required for testing the newest communications standards, which consider multiple channels working at higher data rates. In this paper, a new reconfigurable architecture(More)
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the(More)
In this paper, a novel control generation methodology based on the Polytope Model is proposed for the QR decomposition problem mapped onto systolic array processors. Many FPGA accelerator implementations for QR decomposition based on array of processors have been studied. However, the design of the control path is one of the greatest challenges in the(More)