Aldo Pena-Perez

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This third-order ΔΣ modulator [1, 2], suitable for high-resolution low-power sensor systems, consumes 140μW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step The DACs use a single resistive divider to generate 32 differential 5b reference voltages. The proposed scheme totally cancels the error caused by(More)
—A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 µm technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/µs(More)
—A low-power switched-capacitor third-order sigma-delta modulator suitable for portable sensor systems is described. The architecture uses only one operational amplifier working in a time-interleaved fashion. The architecture employs swing reduction techniques to limit the swing and the slew-rate requirements of all internal nodes. Realized in a 0.18-m 2P6M(More)
—This paper proposes the use of a digital mod-ulator with pseudorandom variation of coefficients. The method improves PLL-based Fractional Frequency Synthesizer's performance while using a low order digital modulator. The time variant coefficients, in a low order digital modulator, significantly enlarge the pseudorandom output pattern period thus avoiding(More)
A new method that compensates for the low DC gain of nanometre operational amplifiers (opamps) used for high-speed continuous-time (CT) ΣΔ modulators is described. The proposed solution compensates for the integrator's phase error which is a main limitation produced by the low opamp's gain. The method uses a simple auxiliary gain stage and a resistor.(More)
This work proposes a novel topology for a three stages Operational Transconductance Amplifier with feedforward g<sub>m</sub> paths. The proposed solution enhances the amplifier's Gain-Bandwidth product and enables capacitive Miller compensation with no appearance of a Right-Half-Plane zero on its transfer function. The main difference with state of the art(More)
—An incremental ADC for Wheatstone CMOS stress sensor systems is described. A switched-capacitors integrator without switches toward virtual ground avoids spur signals, clock feed-through, residual offset and glitches. The circuit, fabricated in a 0.35-µm CMOS technology, consumes 42 µW at 500-kHz clock and 2.8-V supply. Low speed chopping cancels offset(More)